1. Field of the Invention
The present invention relates to a nonvolatile memory device, and in particular to data protection of a nonvolatile ferroelectric memory device.
2. Description of the Related Art
Recently, a nonvolatile memory, which has a function of retaining data even when powered off, has been realized through the use of a ferroelectric material such as lead zirconate titanate (PZT) exhibiting hysteresis characteristics. Employing such a ferroelectric material in a memory cell, the nonvolatile memory can be achieved with a simple structure. Several examples of the application are disclosed in Japanese Patent Unexamined Publications Nos. 63-201998 and 1-158691 and the paper "A 256 Kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns" (International Solid-State Circuits Conference, ISSCC, Digest of Technical Papers, pp. 268-269, February, 1994).
A ferroelectric memory cell will be described hereinafter based on the above-mentioned publications. FIG. 1A shows the circuit of a ferroelectric memory cell. A memory cell MC consists of a switching transistor Tr and a ferroelectric capacitor C (1-Transistor and 1-capacitor per bit: 1T/1C). The switching transistor Tr has two major electrodes (drain and source) connected to one electrode of the capacitor C and a bit line BL, respectively, and has the gate electrode connected to a word line WL. The other electrode of the capacitor C is connected to a plate line PL.
A read and write operation of the memory cell MC is described referring to FIGS. 1B and 1C. First of all, as shown in FIGS. 1B and 1C, the ferroelectric capacitor C exhibits hysteresis characteristics with respect to a voltage V across the capacitor C. Therefore, 1-bit data is stored in the ferroelectric capacitor C as the difference in polarization P between the point a and the point e for V=0. More specifically, the values 1 and 0 of the 1-bit data may be in correspondence with the state points a and e of polarization P, respectively. This relationship will be employed in the following examples.
As illustrated in FIG. 1B, assuming that the data value 1 is stored in the ferroelectric capacitor C whose polarization state is at the point a. When the switching transistor Tr is forced into conduction (or ON) by applying a high-voltage level (here, the power supply voltage Vcc) to the word line WL and a negative voltage -Ve is applied to the ferroelectric capacitor C through the bit line BL and the plate line PL, the polarization P is changed from the state point a to the state point d via state points b and c. Charge Q1 corresponding to this state transition is transferred between the bit line BL and the ferroelectric capacitor C through the switching transistor Tr. The charge transfer can be detected by a sense amplifier connected with the bit line BL, which means that the data value 1 is read from the memory cell MC. After reading the data from the memory cell MC, the same data "1" on the bit line BL is written back onto the memory cell MC by lowering the voltage of the plate line PL. This write sequence follows the reverse state transition from the state point e to the state point h via state points f and g.
On the other hand, as illustrated in FIG. 1C, in the case that the data value 0 has been stored in the ferroelectric capacitor C whose polarization state is at the point e, the polarization P is changed from the state point e to the state point d via the state point c. Charge Q0 corresponding to this state transition is transferred between the bit line BL and the ferroelectric capacitor C through the switching transistor Tr. The charge transfer can be detected by the sense amplifier connected with the bit line BL, which means that the data value 0 is read from the memory cell MC.
By arranging a lot of ferroelectric memory cells MCs in rows and columns which are connected with sense amplifiers, address decoders and other necessary circuits, a conventional ferroelectric memory device can be realized as described in the above-mentioned publications.
However, if an abrupt voltage is applied to the ferroelectric capacitor C during power-down or power-up, there is the possibility that the data stored in the memory cell MC is damaged. More specifically, assuming that the data value 1 is stored in the ferroelectric capacitor C whose polarization state is at the point a as illustrated in FIG. 1B and then the memory device is powered down. During power-down, if a word line WL abruptly increases in voltage due to a malfunction of the X-decoder, causing the switching transistor Tr to be forced into conduction, then the negative voltage -Ve is applied to the ferroelectric capacitor C on condition that a voltage of the plate line PL is higher than that of the bit line B1 by the voltage Ve. As a result, the polarization P of the ferroelectric capacitor C is shifted from the state point a to the state point d via state points b and c. Therefore, after power-down, the polarization P settles at the state point e corresponding to the data value 0, which means that the contents of the memory cell MC is damaged.